Coherency Verification Engineer - remote job

TechBiz Global is hiring a Coherency Verification Engineer. The role sits in IT and programming and is fully remote. The company places no restriction on where the candidate lives, so you can apply from anywhere.

The advert singles out Python, so experience with that one tool is what will decide it.

The employer did not publish a figure; that is settled at interview. The advert sets no condition on working hours.

This vacancy passed an automated check: the list excludes any advert requiring a foreign work permit, visa sponsorship, a particular citizenship, or residence in a specific country.

At TechBiz Global, we offer specialized recruitment services to our premier clients. We are currently looking for a Coherency Verification Engineer to enhance one of our client’s teams. If you are eager to expand in a cutting-edge setting, this role might be ideal for you. Key Responsibilities:

- Ensure the accuracy of intricate digital designs at the RTL stage, adhering to the established architecture and design guidelines. - Design and sustain verification frameworks using SystemVerilog and UVM. - Formulate, implement, and troubleshoot test strategies for both block-level and system-level verifications. - Focus on the validation of coherent systems, particularly concerning cache-related features and interconnect performance. - Confirm the correctness of designs that involve CHI protocols, cache configurations, coherency protocols, and overall system interactions. - Execute and oversee simulations, regressions, and failure analysis with industry-standard verification software. - Employ formal and dynamic verification techniques to pinpoint design flaws early on. - Utilize scripting tools like Python, Perl, Bash, or TCL to streamline verification processes and regression testing. - Engage closely with the architecture, design, and verification teams to interpret specifications, refine requirements, and address challenges. - Monitor, document, and report on verification advancements, bug occurrences, coverage metrics, and technical risks. - Support the ongoing enhancement of verification protocols, tools, and best practices.

Qualifications:

- Advanced degree (Master’s or PhD) - Fluent English (C1 level) - At least 8 years of industrial experience - Expertise in SystemVerilog and UVM - Competence in scripting languages (Python, Perl, Bash, TCL) and regression tools - Background in simulation and simulation tools - Familiarity with version control practices and tools (git, svn) - Proven experience in block-level and sub-system or top-level verification - Knowledge of formal and dynamic verification methods - Demonstrated problem-solving capabilities and meticulous attention to detail - Strong interpersonal and collaborative skills - Understanding of CHI protocols - Insight into cache structures and parameters - Experience in verifying coherent systems

Originally posted on Himalayas